Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates
نویسندگان
چکیده
منابع مشابه
Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates
In this paper, we present the Implementation of the Binary Multiplier on CPLD using Reversible logic gates. These circuits have been simulated on Active HDL and synthesised on Xilinx web pack 5.1 software.
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ژورنال
عنوان ژورنال: IOSR Journal of Electronics and Communication Engineering
سال: 2017
ISSN: 2278-8735,2278-2834
DOI: 10.9790/2834-1201034042